1. Field of the Invention
The invention is directed to a memory apparatus and more particularly, to a flash memory apparatus and a data reading method thereof.
2. Description of Related Art
In a conventional flash memory array, memory cells are arranged in a rectangular array formed by rows and columns, and memory cell transistors are configured at intersections of the rows and the columns. In each transistor, a drain is connected to a corresponding bit line, a source is connected to a drain of an array source discharge transistor through an array source line, and a gate is connected to a word line.
A flash memory allows a programming, a reading or a erasing operation performed based on bulks, sectors or pages. Generally speaking, a memory cell has a metal oxide semiconductor (MOS) structure, and when a floating gate of the memory cell does not store any electric charge (i.e., when written data is “1”), the memory cell is normally on when performing a reading operation. When the floating gate stores electrons (i.e., when the written data is “0”), the memory cell is normally off when performing a reading operation.
When a reading operation is performed on the flash memory, a reading level of voltage is applied to a control gate of a selected memory cell, and a low level is applied to a drain bit line of a selected transistor. Whether the memory cell is turned on to a source line is determined according to a threshold voltage of the memory cell, and thereby, a level of the bit line is sensed, and data stored in the memory cell is determined. When the data stored in the memory cell is “1”, a current appears on the bit line corresponding thereto. Generally, sources of the memory cells in the same page group of the flash memory array are connected in common to a source discharge transistor, and the current generated by reading the memory cells flows to a ground of the source discharge transistor. When most of the data stored in memory cells of the page group is “1”, the size of the current flowing from the page group would probably exceed the maximum discharge current that the source discharge transistor can achieve. Thus, the size of the current flowing from the memory cells in the page group is limited, and as a result, correctness of interpreting data content stored in the memory cells and speed of reading the data will be affected.